The present invention is related to a data processing system having input/output channels, control units each for controlling peripheral devices, and a dynamic switch between the channels and the control units, and is more particularly related to controlling the power sequencing of a control unit, either under local control or under remote control, by a channel through the dynamic switch.
Various switches such as cross-point switches are known for establishing connections between data lines. Such switches are useful in establishing point-to-point connections between an input/output (I/O) channel of a data processing system and an I/O peripheral device or control unit.
Georgiou, Parallel Interface Switching Mechanism, pp 4690-4692, IBM Technical Disclosure Bulletin, Vol. 27, No. 8, January, 1985, discloses utilizing high-speed cross-point switching chips in multiple parallel interface switching mechanisms. A controller is referred to but not shown which is used to set up connections on the switching chips in order to establish paths between channels and control units.
U.S. Pat. No. 4,074,142 to Jackson for Optical Cross-Point Switch issued Feb. 14, 1978 and discloses an optical cross-point switch for connecting any of a multiplicity of input signals to any of a multiplicity of output lines. Electrical signals are converted to optical signals by light emitting diodes. The light from each light emitting diode is focused on photosensor means to convert the optical signals back to electrical signals. An input and output address decoding circuit selects one light emitting diode to be coupled to one photosensor to make a switch connection. The address information is transmitted to the optical switch via an address bus.
U.S. Pat. No. 4,562,533 to Hodel et al. for Data Communications System to System Adapter issued Dec. 31, 1985 and discloses a data processing system having a dynamic channel exchange and a plurality of central systems. Each of the central systems has at least one serial channel control processor. The dynamic channel exchange provides switching logic for permitting each of the plurality of central systems access to a plurality of peripherals coupled to the dynamic channel exchange. The data processing system further includes an adapter which is connected to the dynamic channel exchange for providing communications between any pair of central systems.
U.S. Pat. No. 4,605,928 to Georgiou for Fault-Tolerant Array of Cross-Point Switching Matrices issued Aug. 12, 1986 and discloses a cross-point switch in which it is possible to have bi-directional operation for allowing data flow in both directions.
U.S. Pat. No. 4,630,045 to Georgiou for Controller for a Cross-Point Switching Matrix issued Dec. 16, 1986 and discloses a switching matrix controller which interprets a request for connection or disconnection, determines if it is possible, selects a path through the matrix and sends control signals to the matrix to make the connection or disconnection. The status of the switching array is checked when making the connection or disconnection.
U.S. Pat. No. 4,635,250 to Georgiou for Full-Duplex One-Sided Cross-Point Switch issued Jan. 6, 1987 and discloses a one-sided cross-point switching chip which may be operated in a full duplex mode wherein the direction of information flow or electrical signals on the internal vertical lines or the interconnection lines can be in different directions, depending upon which external lines are to be interconnected.
U.S. Pat. No. 4,641,302 to Miller for High Speed Packet Switching Arrangement issued Feb. 3, 1987 and discloses a circuit arrangement for switching serial data packets through a network to one of a plurality of possible outgoing lines. The incoming serial data is in packets wherein each packet includes a header portion containing an address indicative of which one of a plurality of outgoing lines the data packet should be routed to.
U.S. Pat. No. 4,692,917 to Fujioka for Packet Switching System issued Sep. 8, 1987 and discloses a packet switching system having a packet handler for analyzing a header of each incoming packet and deciding the outgoing route of the packet. The packet also includes a packet closing flag which causes the packet handler to release the connection.
U.S. Pat. No. 4,703,487 to Haselton et al. for Burst-Switching Method for an Integrated Communications System issued Oct. 27, 1987 and U.S. Pat. No. 4,771,419 to Graves et al. for Method of and Switch for Switching Information issued Sep. 13, 1988. Both of these patents disclose switching networks for switching data wherein a header contains an address for making a connection and a termination character or characters for breaking the connection.